1. Field of the Invention
The invention relates to the field of MOS random-access memories.
2. Prior Art
Numerous metal-oxide-silicon (MOS), random-access memories (RAMs) are known in the prior art, including memories which employ load transistors which operate in a depletion mode. These memories are typically fabricated on a single silicon substrate, and in static memories, employing bistable circuits for memory cells. A plurality of Y-lines or column lines are used both for sensing information stored in the cell (reading) and also to write information into the cells. These column lines communicate with a single read bus which in turn supplies output data through an output buffer.
To provide high speed operation, the capacitance associated with the column lines must be minimized. However, in prior art memories the capacitance of any particular column line often includes capacitance associated with the read lines, and even, capacitance associated with other column lines. This added capacitance reduces the rate at which information may be read from the cell, and hence reduces the overall access time of the memory. As will be seen, the present invention provides a column sense amplifier which de-couples the unselected column lines from the read bus, and furthermore, which permits reliable sensing of small voltage changes on the column line.
Another problem encountered in prior art memories, particularly as access time is decreased, is that of multiple selection. Often address buffers are utilized to generate the complement of an address, thus, for each address bit its complement is also used in the decoders. However, if the complement bits are delayed from the "true" address bits (because of delays in the address buffers) multiple selections can occur. As will be seen, the present invention provides an address buffer in which the complement of an address bit is generated simultaneously with the buffered true address bit.